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KG Balanced Dynahi build discussion thread

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Hmm, relatively consistent with my measurements but way off from what the datasheet states. Wonder if I am not reading the datasheet correctly or something else is amiss?

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Maybe just measure the Idss and the pinch-off voltage instead? You are never going to use these at such low circuit parameters...

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12 hours ago, luvdunhill said:

That’s because it’s a JFET. Most (all?) are symmetrical.

If you don't mind downloading a 25mb pdf, the National FET Databook actually shows the dies. Some aren't perfectly symmetrical, so while they'll work in either configuration, I'm guessing they could perform slightly differently if D and S are flipped (e.g. process 88 shows more surface area for the S than D-- might impact gm?).

http://bitsavers.trailing-edge.com/components/national/_dataBooks/1977_National_FET_Databook.pdf

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For Jfets Idss measures I prefer use this:

matching_jfet.png

 

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I compared them on a curve tracer and they were identical both directions. So, seemed good enough for me.

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So I rigged together the test circuit both Jose and Chris suggested that used a 12VDC supply and measured the whole batch of 2SK170BL and 2SJ74BL (12 each).

The 2SK170BL IDSS measured between 7.7 - 11.2 mA, the 2SJ74BL measured between 7.0 - 11.0 mA but mostly between 8.0 - 11mA. Toshiba datasheet states 6 - 12mA for BL grade.

The good news is that the relative measurements between samples are consistent with those from the ATMega 328 tester. 

I am pleasantly surprised that I should be able to find 4 pairs of K170 within 3% and 2 pairs of SJ74 within 1% and another 2 pairs within 5% of these random samples. Not great but OK. Unfortunately the match between P and N channel pairs are not nearly as good.

Forgot to mention; if you are going to do this, make sure you do it in a constant ambient temperature environment and you sit a good 2 + feet from the sands being measured. For a while the measurements were jumping all over the place only to find out it was caused by my radiant body heat. Christ!

 

7D980444-1C9D-43EF-9D8D-BE2C8B5CE34F.jpeg

Edited by mwl168
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So I am confused now with the JFET - BJT pin mapping looking at the photos and posts in this thread.

It's clear that BJT Base -> JFET Gate.

Knowing that the Toshiba JFET Drain and Source are interchangeable, which one is theoretically correct? 

BJT Collector -> JFET Source,  BJT Emitter -> JFET Drain 

OR

BJT Collector ->JFET Drain,  BJT Emitter -> JFET Source   

Edited by mwl168

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N channel on bottom (2SK170)

P channel on top (2SJ74)

Emitter – (E)      >>     Source – (S)

Base – (B)         >>     Gate – (G)

Collector – (C)  >>     Drain – (D)

vfxKDfWl.jpg

Edited by jose

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49 minutes ago, jose said:

N channel on Right (2SK170)

P channel on Left (2SJ74)

Emitter – (E)      >>     Source – (S)

Base – (B)         >>     Gate – (G)

Collector – (C)  >>     Drain – (D)

vfxKDfWl.jpg

Thanks Jose.

I think you meant P channel (J74) on top and N channel (K170) on bottom? 

Also, looking at the photo, it looks like the D pin of the JFET is inserted into the E slot of the socket?

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In my Dynalo. I think you can see it better here:

 

NnE0lVml.jpg

7 minutes ago, mwl168 said:

I think you meant P channel (J74) on top and N channel (K170) on bottom? 

 

Yes, you are right I rotated the photo when inserting it in the post. 

 

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Thanks Jose. 

It still looks to me that the drain pins are inserted into the emitter slots?

Edited by mwl168

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Sorry Michael. Last night was very late when I answered

I believe that the Drain pin is correctly connected to the Collector pin.

Edit:  Maybe I'm confused ... I need to look again at the transistor meter to be able to identify the pins.

To be connected to the opposite, what makes clear is that they work

 

Edited by jose

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When I did the adapters (and built my SS Dynalo), I had looked into this and this is what I used:

C -> D

B -> G

E -> S

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Base on the Toshiba 2SK170 and 2SJ74 datasheet, with the marking side of the JFET facing you, the left-most pin is the drain and the right-most pin is the source. 

 

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55 minutes ago, mwl168 said:

Base on the Toshiba 2SK170 and 2SJ74 datasheet, with the marking side of the JFET facing you, the left-most pin is the drain and the right-most pin is the source. 

 

Yes, I checked my amps and mi notes and i was wrong. I've been using them like that for a while. Now, we know empirically that it works inverted.

I found this photo. It was the one that confused me: 

What a shame!!!! :sadcat::sadcat:

 
 
On ‎10‎/‎25‎/‎2017 at 2:07 AM, congo5 said:

I saved that pic but can't find it

here is my SSDynalo with jfets

N channel on top

P channel on bottom

202910_HDR.jpg

 

 

Edited by jose

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I rotated the Jfets. I don´t notice any change. Good opportunity to check Bias, voltage, tighten connectors ... everything is correct.

The only thing I have noticed is that the plates have lost a bit of bright green due to the heat.

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On 12/30/2013 at 6:10 PM, kevin gilmore said:

are you sure those are 2pf caps, not 2uf caps. because that would definitely kill all the gain.

 

also mospec semiconductor...  I use real Motorola parts...

 

 

edit: yep 2uf would take the gain down to about -50db at 1khz.

For this compensation cap in the feedback circuit, does it pay to use Mica caps instead of ceramic caps?

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On 7/6/2019 at 6:01 PM, mwl168 said:

For this compensation cap in the feedback circuit, does it pay to use Mica caps instead of ceramic caps?

If you use MLCC C0G/NP0 grade, I doubt the difference will be audible. Or, MLCC will be even better. At least amb votes for them:

https://www.amb.org/forum/about-building-beta24-t3688-10.html?hilit=mica#p34356

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It took 5 months but my Dynahi is making music now.

This one uses matched 2SK170/2SJ74 in place of the THAT340. PSTA06/56 in place of MPSW06/56. Gain is set at 5 and running 30VDC rails.

Aside from matching the sands, the most challenging part for me was to figure out how to adjust the amp which I will document in a separate post. The build took a long time for various reasons but was relatively uneventful. It helps that I read this thread back and forth and took notes along the way.

Many thanks to Kevin and to those that have contributed much valuable and crucial information. 

 

Dynahi.JPG

Edited by mwl168
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My build uses the latest board version that uses PZTAx6 SMD parts.  Power supply is 2 GRLV set for  +/- 30VDC rails with 2 100VA transformers. 

Here are the detail steps I went through to adjust and bias my Dynahi. I gathered the information from reading this thread and other Dynahi build discussions on the web. Also consulted Kevin and reference the schematic.

I hand measured and matched all resistors, LEDs and transistors before soldering. I only matched the output devices (MJF15030/MJF15031) at very low current but this seems to work out fine at the actual working current (75mA). I replaced one that was about 5% off. The rest are all within 1.5 % of each other. I use matched 2SK170/2SJ74 pairs to replace the THAT340. They are BL grade. Feedback resistors (R52, R56) are 50K (200K on silkscreen) and I use 100R for R23, R24 (50R on silkscreen), 680R for R1, R4 (500R on silkscreen). This combination of R1/R4, R23/R24 works great for my target bias current of 75mA per output device. To bias the output devices for the desired current, it’s necessary to pick the right combination of R1/R4 and R23/R24. Higher R23/R24 resistance increases bias current while higher R1/R4 resistance shifts the bias adjustment range downward. As Kevin has warned more than once, do not test this amp without proper heatsink. The MJF15030/15031 is only rated at 2W maximum dissipation in 25C ambient temperature.

I took the following steps to bias and adjust the amp:

Step 1 - before powering up the amp:

Set RV3 and RV4 in their exact middle value. The Bourns trim pots I use have a 10% tolerance. I measured R9/R10, R11/R12 (100R resistors on top and below RV3 and RV4) to ensure RV3 and RV4 are both centered. RV3 and RV4 are located on the PCB right next to the THAT340.  

Set RV1 and RV2 to their maximum resistance so the amp is biased at the lowest possible output current. I did this by measuring the resistance of R1 and R4 (the 500R on the PCB right next to RV1 and RV2). On my amp, they are about 640R.

On my build, I mounted RV2 backwards (in regard to the silkscreen) so turning both RV1 and RV2 adjustments clockwise decrease their resistance.

Step 2 – power up check:

Power on the amp and measure bias current (indicated by the voltage drop across the bank of 20R resistors) and output DC offset. With my amp at cold start and before any adjustments, the bias current is about 34mA and the output offset measured to ground is -1 VDC on one board and -0.5 VDC on the other. The DC offset between O+ and O- is 19mV and 25mV. This step is a sanity check to see if anything is out of whack.

Let the amp warm up to steady working temperature before proceeding to next step while taking periodic measurements and checking the heatsink temperature. It takes 30 minutes or more for the amp to reach steady temperature.

For the following steps, make the adjustments slowly and gradually and allow time for the amp to settle following each adjustment.

Step 3 – compensate for transistors mismatch in the input stage:

Adjust RV3 and RV4 so the voltage drop across R7 and R8 are the same and the voltage drop across R13 and R14 are the same. This adjustment is tricky and delicate. Adjusting either RV3 or RV4 affects the voltage drop across all 4 resistors (R7, R8, R13, R14).  Also the adjustment is made to a 10K trim pot (pre-adjusted to 5K) parallel to a 100R resistor. The resistance change is relatively small at first in relation to the turns of the trim pot. I adjusted RV3 and RV4 in small and equal amount in turn to get to equal voltage drop between R7/R8, R13/R14. Be patient and be careful!   This adjustment affects the DC offset between O+ and O-.  

Step 4 – biasing output sections:

Decreasing the resistance of either RV1 or RV2 will increase the current of ALL the 16 output devices on the board. At the same time, decreasing RV1 resistance will push the output DC offset (measured to ground) more negative while decreasing RV2 resistance will push the output DC offset more positive. Adjust RV1 clockwise to increase the bias, say 20mA at a time. The output DC offset to ground will go more negative at the same time. Then adjust RV2 clockwise (CCW if RV2 is mounted in accordance to the silkscreen) to bring the output DC offset close to 0mV (the bias current will increase at the same time). Repeat these two adjustments back and forth until you reach your desired bias current while keeping the output offset as close to 0mV as possible. The offset between O+ and O- is not affected by RV1/RV2 adjustment and will remain very stable through the process while the offset to ground will drift quite a bit. It’s normal.    

Step 5 – nulling the offset between O+ and O- if needed and/or desired: 

Adjust RV3 and RV4 in a convergent fashion (one clockwise, the other counter-clock wise) to bring the offset between O+ and O- to 0 V.  

I consider this step 5 optional unless the offset between O+ and O- is excessive and cannot be taken care by the servo.

I did not do step 5 on my amp since, following step 3 and 4, without the servo, the offset is steady at 23mV on one channel and 25mV on the other and not likely to hurt anything. I can always engage the servo if desired.

I have tried other methods of adjustment including one that skipped Step 3. The difference is that, with step 3, I end up with more uniform output current across all 16 output devices, generally within 1.5% of each other. When I skip step 3, while the current between the PNP and NPN banks on each phase is within 1.5% or so, the current variance between non-inverted and inverted phases is about 8%. I did not try very hard but frankly my wooden ears could not tell the difference between the outcome of the two methods. Maybe someone with a scope can see the difference. I also consulted with Kevin and he does not feel strongly if there is a right or wrong method either.    

One more thing, this thing runs hot! By my calculation, running +/- 30VDC rails and 75mA bias, each output device is dissipating 2.19W. That’s about 35W of heat needing to be dissipated by the heatsink per board. It’s a monster of a headphone amp!  

Edited by mwl168
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nice to see your success, it's the amp i like a lot with my power hungry magentoplanar headphones. after the that340 i tested the trendsetter lsk489/ls689 but at the end i enjoyed the 2sc3381/2sa1349 the most, quite shure that with the 2SK170/2SJ74 this amp performs superb. let us see the amp when it in its chase ;-). well done

Edited by rumina

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I'm glad you finished the amplifier. Good job with the adjustment tutorial. 

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contgats !

6 hours ago, mwl168 said:

It took 5 months but my Dynahi is making music now.

This one uses matched 2SK170/2SJ74 in place of the THAT340. PSTA06/56 in place of MPSW06/56. Gain is set at 5 and running 30VDC rails.

Aside from matching the sands, the most challenging part for me was to figure out how to adjust the amp which I will document in a separate post.The build took a long time for various reasons but was relatively uneventful. It helps that I read this thread back and forth and took notes along the way.

Many thanks to Kevin and to those that have contributed much valuable and crucial information. 

 

Dynahi.JPG

 

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Almost done casing the Dynahi. The input XLR sockets are temporary, waiting for the Neutrik ones to arrive.

Also, cased the dual GRLV PSU which I will be using for both the SUSY Dynahi and balanced CFA. Two Antek 100VA transformers and the GRLVs are set for 30VDC rails.

 

SS Dynahi 3.JPG

SS Dynahi 2.JPG

SS Dynahi amp.JPG

Dynamic amp PSU 2.JPG

SS Dynahi 1.JPG

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