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KG Balanced Dynahi build discussion thread

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Hmm, relatively consistent with my measurements but way off from what the datasheet states. Wonder if I am not reading the datasheet correctly or something else is amiss?

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Maybe just measure the Idss and the pinch-off voltage instead? You are never going to use these at such low circuit parameters...

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12 hours ago, luvdunhill said:

That’s because it’s a JFET. Most (all?) are symmetrical.

If you don't mind downloading a 25mb pdf, the National FET Databook actually shows the dies. Some aren't perfectly symmetrical, so while they'll work in either configuration, I'm guessing they could perform slightly differently if D and S are flipped (e.g. process 88 shows more surface area for the S than D-- might impact gm?).

http://bitsavers.trailing-edge.com/components/national/_dataBooks/1977_National_FET_Databook.pdf

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For Jfets Idss measures I prefer use this:

matching_jfet.png

 

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I compared them on a curve tracer and they were identical both directions. So, seemed good enough for me.

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So I rigged together the test circuit both Jose and Chris suggested that used a 12VDC supply and measured the whole batch of 2SK170BL and 2SJ74BL (12 each).

The 2SK170BL IDSS measured between 7.7 - 11.2 mA, the 2SJ74BL measured between 7.0 - 11.0 mA but mostly between 8.0 - 11mA. Toshiba datasheet states 6 - 12mA for BL grade.

The good news is that the relative measurements between samples are consistent with those from the ATMega 328 tester. 

I am pleasantly surprised that I should be able to find 4 pairs of K170 within 3% and 2 pairs of SJ74 within 1% and another 2 pairs within 5% of these random samples. Not great but OK. Unfortunately the match between P and N channel pairs are not nearly as good.

Forgot to mention; if you are going to do this, make sure you do it in a constant ambient temperature environment and you sit a good 2 + feet from the sands being measured. For a while the measurements were jumping all over the place only to find out it was caused by my radiant body heat. Christ!

 

7D980444-1C9D-43EF-9D8D-BE2C8B5CE34F.jpeg

Edited by mwl168
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So I am confused now with the JFET - BJT pin mapping looking at the photos and posts in this thread.

It's clear that BJT Base -> JFET Gate.

Knowing that the Toshiba JFET Drain and Source are interchangeable, which one is theoretically correct? 

BJT Collector -> JFET Source,  BJT Emitter -> JFET Drain 

OR

BJT Collector ->JFET Drain,  BJT Emitter -> JFET Source   

Edited by mwl168

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N channel on bottom (2SK170)

P channel on top (2SJ74)

Emitter – (E)      >>     Source – (S)

Base – (B)         >>     Gate – (G)

Collector – (C)  >>     Drain – (D)

vfxKDfWl.jpg

Edited by jose

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49 minutes ago, jose said:

N channel on Right (2SK170)

P channel on Left (2SJ74)

Emitter – (E)      >>     Source – (S)

Base – (B)         >>     Gate – (G)

Collector – (C)  >>     Drain – (D)

vfxKDfWl.jpg

Thanks Jose.

I think you meant P channel (J74) on top and N channel (K170) on bottom? 

Also, looking at the photo, it looks like the D pin of the JFET is inserted into the E slot of the socket?

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In my Dynalo. I think you can see it better here:

 

NnE0lVml.jpg

7 minutes ago, mwl168 said:

I think you meant P channel (J74) on top and N channel (K170) on bottom? 

 

Yes, you are right I rotated the photo when inserting it in the post. 

 

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Thanks Jose. 

It still looks to me that the drain pins are inserted into the emitter slots?

Edited by mwl168

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Sorry Michael. Last night was very late when I answered

I believe that the Drain pin is correctly connected to the Collector pin.

Edit:  Maybe I'm confused ... I need to look again at the transistor meter to be able to identify the pins.

To be connected to the opposite, what makes clear is that they work

 

Edited by jose

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When I did the adapters (and built my SS Dynalo), I had looked into this and this is what I used:

C -> D

B -> G

E -> S

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Base on the Toshiba 2SK170 and 2SJ74 datasheet, with the marking side of the JFET facing you, the left-most pin is the drain and the right-most pin is the source. 

 

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55 minutes ago, mwl168 said:

Base on the Toshiba 2SK170 and 2SJ74 datasheet, with the marking side of the JFET facing you, the left-most pin is the drain and the right-most pin is the source. 

 

Yes, I checked my amps and mi notes and i was wrong. I've been using them like that for a while. Now, we know empirically that it works inverted.

I found this photo. It was the one that confused me: 

What a shame!!!! :sadcat::sadcat:

 
 
On ‎10‎/‎25‎/‎2017 at 2:07 AM, congo5 said:

I saved that pic but can't find it

here is my SSDynalo with jfets

N channel on top

P channel on bottom

202910_HDR.jpg

 

 

Edited by jose

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I rotated the Jfets. I don´t notice any change. Good opportunity to check Bias, voltage, tighten connectors ... everything is correct.

The only thing I have noticed is that the plates have lost a bit of bright green due to the heat.

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On 12/30/2013 at 6:10 PM, kevin gilmore said:

are you sure those are 2pf caps, not 2uf caps. because that would definitely kill all the gain.

 

also mospec semiconductor...  I use real Motorola parts...

 

 

edit: yep 2uf would take the gain down to about -50db at 1khz.

For this compensation cap in the feedback circuit, does it pay to use Mica caps instead of ceramic caps?

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On 7/6/2019 at 6:01 PM, mwl168 said:

For this compensation cap in the feedback circuit, does it pay to use Mica caps instead of ceramic caps?

If you use MLCC C0G/NP0 grade, I doubt the difference will be audible. Or, MLCC will be even better. At least amb votes for them:

https://www.amb.org/forum/about-building-beta24-t3688-10.html?hilit=mica#p34356

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