Bespav Posted May 26, 2020 Report Share Posted May 26, 2020 Keeping in mind Kevin Gilmore's design rules i have insomnia about stabilizing common mode of JFET input stage without sacrificing CMRR or straight referencing it to the amplifier/source ground. So, check attached schematic. While keeping straightforward signal flow aka "Gilmore's gesign rule" it also have second control loop which helps SuSy amps to maintain output common mode near ground potential. Quote Link to comment Share on other sites More sharing options...
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