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Group Build: Dynafet


luvdunhill

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The design goal is 75 ma per fet

well, okay, but I for one interpreted your comment in post #19 as designing towards 150mA:

HeadWize: DIY Workshop > My newest in the dyna series

"If you run the default of 150 ma per fet, the 2 ohm resistors

are fine."

In hindsight, I see how that comment could have been misconstrued in a number of different ways.

All that said, I think more than 75mA is better. I know there are quotes from Borbely who uses these FETs in one of his design that many of his customers preferred them at > 100mA, and I tend to agree. Here's a quote from his old website:

"More is Better (sometimes)! Although the fact is well known that MOSFETS require a lot of current to sound super, I believed that the suggested 40mA or so in the output stage was optimal. Until one of our customers suggested to try more. Mind you the tiny heatsink we are supplying with the Kit can

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How did that happen?

I had to have a minor in grad school and chose Comp Sci. The use of computers to gather and process lab data was just starting and I thought it was a good minor. We also had a foreign language requirement, and knowledge of a computer language fulfilled it. After a couple of years as a physiology grad student, I was tired of killing things and didn't really like the future path ahead of me. So I made my minor my major. It was one of the smartest moves I've made, probably only second to deciding to go to work for Stratacom rather than ACC (Advanced Computer Communications) in 1996.

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I had to have a minor in grad school and chose Comp Sci. The use of computers to gather and process lab data was just starting and I thought it was a good minor. We also had a foreign language requirement, and knowledge of a computer language fulfilled it. After a couple of years as a physiology grad student, I was tired of killing things and didn't really like the future path ahead of me. So I made my minor my major. It was one of the smartest moves I've made, probably only second to deciding to go to work for Stratacom rather than ACC (Advanced Computer Communications) in 1996.

ahh thats pretty cool. And its pretty funny that knowledge of a comp language fulfilled a foreign language requirement :D

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It actually made sense. The foreign language requirement was from the old days when many research papers were published in a language other than English (usually German, French or Russian). By the time I entered grad school in 1976 you could find pretty much everything in English. So knowing a computer language was actually more useful for research than knowing a foreign language.

In almost 30 years of being a s/w engineer, I've studiously avoided learning Cobol.

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So, I am now interested in 75-100ma per FET biasing, and not the 150ma that was previously discussed. Hopefully the parts selection will accomodate that.

Also, at 4 fets per board recommended, did we end up getting charged for double the needed FETs, and is a refund for the difference in order?

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So, I am now interested in 75-100ma per FET biasing, and not the 150ma that was previously discussed. Hopefully the parts selection will accomodate that.

Also, at 4 fets per board recommended, did we end up getting charged for double the needed FETs, and is a refund for the difference in order?

See Kevin's post above. Nothing has changed. Four FETs @ 150mA or 8 FETs @ 75mA. Same heat. I ran them harder just as a proof of concept, but this has always been the recommended current.

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but the design is for 75ma per FET, irregardless of 4 or 8 FETs per board, is it not?

Heat is an issue, but what do you loose by only using 4 FETs per board (the original design) compared to 8 per board?

no. The original design was 150mA per FET with 4 devices. See the posts above. Once you doubled to eight, it requires double the heat sink. Instead, Kevin halved the bias so he didn't have to go out and by a larger heat sink, or go from 2 boards per heat sink to one, or run the die temperature way up.

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So its not 4 fets at 75mA for a total of 300mA?

I thought that's what "For a total power supply of 300ma at 60 volts which is 18 watts." means.

no, four pairs at 75mA through each pair. Remember, current is calculated (edit: maybe "defined" is a better word, I dunno) from rail to rail. So, if one n-ch flows 75mA then the other complimentary p-ch device flows 75mA.

Edited by luvdunhill
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no. The original design was 150mA per FET with 4 devices. See the posts above. Once you doubled to eight, it requires double the heat sink. Instead, Kevin halved the bias so he didn't have to go out and by a larger heat sink, or go from 2 boards per heat sink to one, or run the die temperature way up.

Ok, I stand corrected.

So it still seems 4 per board is the optimal for regular headphones,

especially if the FETs sound better at 100-150ma bias.

How many FETs did we end up buying into?

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no, four pairs at 75mA through each pair. Remember, current is calculated (edit: maybe "defined" is a better word, I dunno) from rail to rail. So, if one n-ch flows 75mA then the other complimentary p-ch device flows 75mA.

I dunno how to explain it. Maybe someone else can better.

But, this calculation is fail:

18W / 60V = 300mA / 8 FETs = 37.5mA per FET

this calculation is win:

18W / 60V = 300mA / 4 FET pairs = 75mA per FET

Then power per device is 75mA * 30V. And with 75mA * 30V * 8 devices = 18W we're back to where we started.

Edited by luvdunhill
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all this is way above my head, but as someone who will, at most, run a stax box from it, what is the lowest these can be biased for purely headphone use?

Gobs of power and massive quantities of heat are not required in my case. Is there a way of running this at a lower power spec which won't affect the sound?

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So where are we at this point?

How about a summary of the goings on and where we are headed?

We need to finalize the production boards and place the order. When we do this is really dependent on how much feedback we as a team want from Kevin and digger945. It probably makes sense to get as much feedback as possible from the both of them. I've made my suggestions in this thread and have sorta moved on to other things that are on my plate. Whether or not all the suggestions are implemented is really up to j4cbo I guess, and how willing he is to comb back through the thread and meticulously pick up all the comments and suggestions :) ... as he's the one that will implement the changes and feature requests.

Once I receive the boards, I'll send out the boards with the matched devices. This includes the JFETs, the BJTs and the MOSFETs. There is still a little bit more matching to do, probably 40 hours or so. I don't even want to think how much time I've already spent...

That's about it I think.

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I'm still tinkering around with the Vbe multiplier and some higher values for the output resistors. So far so good, I just finished rebuilding the multiplier on my own proto board and have some much better results now using 2.2k resistors and 10k trimmer. I have some parts on order that will be in the middle of next week to finish up here. I would like some input as to changing the input bias trimmers(10k's) and the 20k trimmer in the middle of the Vbe, to something smaller and not as touchy, in series with a position for a resistor. This will allow much more flexibility in tuning and allow more precise control over the trimmers. For example instead of 10k maybe a 1k trimmer in series with a 9k resistor.

Also I'm waiting to see how it goes with Kevin, it is his design.

It's coming along. Slow, but progress each day.

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